1. Field of the Invention
The present invention relates to metal oxide semiconductor field effect transistor (MOSFET) circuits and, more particularly, to a buried contact used for source and drain interconnects.
2. Description of the Related Art
Very large scale integration (VLSI) has allowed the semiconductor industry to reduce cost while still increasing performance of advanced integrated circuit devices. This trend has been fueled mainly by the ability of the semiconductor industry to reduce the size of structures within devices, thus producing denser circuits. Photolithography advancements in the form of more advanced cameras, as well as more sensitive photoresist materials, have played a major role in the ability to create smaller images on semiconductor chips. In addition, developments in plasma technologies have allowed submicrometer images in photoresist to be transferred accurately to underlying materials, via the use of anisotropic reactive ion etching (RIE). The use of ion implantation and low pressure chemical vapor deposition (LPCVD) have also been responsible for the creation of smaller, faster integrated circuit devices.
Specific structure and processes have also contributed to the reduction in device sizes. A technique for creating submicrometer sidewall images, and the ability to transfer these submicrometer images to underlying materials, has been described by Ogura, et al., in U.S. Pat. No. 4,648,937. A major application of the Ogura invention has been the insulator sidewall passivation of polysilicon gates, allowing for decreased spacing between the polysilicon gate and the source/drain contacts to be realized. In another attempt to reduce drain size, Lu in U.S. Pat. No. 5,086,017 has presented a method for reducing the amount of source/drain area needed for metal contacts.
Another method used to reduce device size has been the buried contact process for the source and drain elements of MOSFETs. This process connects a doped source/drain region of a MOS device to an intermediate layer consisting of polysilicon or another conductive material and then connects the intermediate layer to a metal or other conductive layer, thereby forming a contact to source/drain regions through a layer of an intermediate conductive material. The contact between the polysilicon and metal is usually made over one of the thick field oxide regions, thus preserving area on the substrate. A conventional process for forming a buried contact to a source/drain region within a MOS device circuit, as well as the contact formed by that process, are illustrated in FIGS. 1-7 of the present application. Referring first to FIG. 1, a P-type substrate 10 has a field oxide region 12 on its surface to isolate active device regions, a gate oxide layer 14 over the illustrated active device region and a thin (.about.800 .ANG.) layer of polysilicon 16 over the entire surface of the device. The buried contact will be formed on the surface of the substrate 10 adjacent the field oxide region 12 of the device. A photoresist mask 18 is formed over the thin polysilicon layer 16 to have an opening 20 extending laterally away from the field oxide region 12. The portion of the polysilicon layer 16 exposed by the opening 20 in the photoresist mask 18 is removed by etching, the exposed portion of the gate oxide 14 is removed by additional etching and then the photoresist mask is removed by ashing to provide the structure shown in FIG. 2.
A second layer of polysilicon 24, typically thicker than the first polysilicon layer 16 as shown in FIG. 3, is deposited over the device so as to be in contact with the first polysilicon layer 16 and the exposed portion 22 of the substrate. A mask 26 is formed over the second polysilicon layer 24. The mask 26 is formed with an opening 28 that will be used to define in part the lateral extent of the MOSFET gate electrode as well as the source/drain region of the MOSFET device. The portion of the polysilicon layer 24 exposed within the mask opening 28 is etched, followed by the portion of the first polysilicon layer 16 within the mask opening 28, and then the gate oxide within the mask opening 28 is etched. During this process, a notch 30 (shown in FIG. 4) is generally formed near the edge of the polysilicon gate electrode and extending below the surface of the substrate where the substrate is not covered by the gate electrode and gate oxide. The mask 26 is then removed to produce the structure illustrated in FIG. 4. A thin layer of oxide (not shown, 200 to 300 .ANG.) is then grown over the surface of the of the polysilicon layer 24 and over the surface of the source/drain region 34.
Ions 32 are implanted into the polysilicon layer 24 and into the exposed portion of the substrate to form the more lightly doped portion of a lightly doped drain (LDD) structure 34. A layer of oxide 42 (2500 to 3000 .ANG.) is deposited over the device (FIG. 5), generally by chemical vapor deposition (CVD), and then an anisotropic oxide etch is performed to provide an oxide spacer 44 alongside the gate oxide 36 and gate electrode 38 and alongside the polysilicon conducting line 40. Note here that the polysilicon gate electrode 38 and polysilicon contact electrode 40 are illustrated as single layers, because they are made up of similar polysilicon layers 16 and 24. After the anisotropic etch back to form the oxide spacers 44 and 46, the more heavily doped section of the LDD source/drain region 34 is formed by implanting ions 48. The portion of doped polysilicon conducting line 40 extending over the surface of the source/drain region 34 provides the buried contact to the source/drain region.
FIG. 7 presents a plan view of the FIG. 6 buried contact structure. The intermediate polysilicon conducting line 40 extends from the field oxide region 12 and onto the surface of the source/drain region 34. Spacer oxide region 46 extends around the periphery of intermediate conducting line 40, at least above the source/drain region 34. Typically, a conducting line formed from a metal such as aluminum is then provided in contact with the layer 40 to provide a connection between the source/drain region 34 and other portions of the circuit. A large overlap between the polysilicon conducting line 40 and the source/drain region 34 is conventionally necessary to provide a sufficiently low contact resistance for the illustrated structure. Because the area of the contact between the polysilicon 40 and the source/drain region 34 determines the resistance of the contact structure, it is typically desirable to increase the size of the contact region. However, this makes the size of the cell undesirably large. In addition, the resistance of the illustrated contact structure varies with changing contact size, so that the resistance of the illustrated structure varies undesirably with alignment and other types of errors.
In general, although buried contact schemes are useful in reducing device sizes, schemes such as that illustrated in FIGS. 1-7 are complex, resulting in increased costs per chip. It is accordingly preferred to provide a simpler and less complex process for obtaining buried contacts to the source and drain regions in advanced MOSFET circuits.